Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 306

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Table 156. DMA X List Address Register High (DMAxLARH)
Table 157. DMA X List Address Register Low (DMAxLARL)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
External DMA Signals
R/W
R/W
7
0
7
0
Writing the DMAxLARL register causes the DMA to enter linked list mode.
Two external pins are associated with each DMA channel capable of external transfers
(Channel 3 does not have external DMA capability). They are active Low DMAxREQ and
DMAxACK signals. DMAxACK signals are outputs and DMAxREQ are inputs.
DMAxREQ must be asserted for a minimum of one system clock period to generate one
DMA transfer. DMAxREQ is left asserted for multiple transactions and deasserted once
DMAxACK asserts for the last appropriate transfer.
R/W
R/W
6
0
6
0
FFE41EH, FFE42EH, FFE43EH, FFE44EH
FFE41FH, FFE42FH, FFE43FH, FFE44FH
R/W
R/W
5
5
0
0
P R E L I M I N A R Y
R/W
R/W
4
0
4
0
DMAxLARH
DMAxLARL
R/W
R/W
3
3
0
0
R/W
R/W
2
0
2
0
Product Specification
ZNEO
R/W
R/W
1
1
0
0
DMA Controller
Z16F Series
R/W
R/W
0
0
0
0
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