Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 210

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
Caution:
10 = TRANSMIT ONLY Mode
11 = TRANSMIT/RECEIVE Mode
BRGCTL—Baud Rate Generator Control
The function of this bit depends upon ESPIEN1,0. When ESPIEN1,0 = 00, this bit allows
enabling the BRG to provide periodic interrupts.
If the ESPI is disabled (
0 = The BRG timer function is disabled. 
1 = The BRG timer function and time-out interrupt are enabled. 
If the ESPI is enabled:
0 = Reading the Baud Rate High and Low registers returns the BRG Reload value.
1 = Reading the Baud Rate High and Low registers returns the BRG Counter value.
If reading the counter one byte at a time while the BRG is counting keep in mind
that the values will not be in sync. It is recommended to read the counter using word
(2-byte) reads.
PHASE—Phase Select
Sets the phase relationship of the data to the clock. For more information on operation of
the PHASE bit, see
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idles High (1).
WOR—Wire-OR (Open-Drain) Mode Enabled
0 = ESPI signal pins not configured for open-drain.
1 = All four ESPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain
If
function. This setting is used for Multi-Master and/or Multi-Slave configurations.
Reading the Baud Rate High and Low registers returns the BRG Reload value.
Reading the Baud Rate High and Low registers returns the BRG Counter value.
If
disabled.
enabled to provide a Slave SCK timeout. See Slave Abort error description.
Use this setting if the software application is both sending and receiving information.
In MASTER mode software must still write to the Transmit Data register to initiate 
the transfer.
requests
not occur.
Use this setting in MASTER or SLAVE mode when the software application is
sending data but not receiving. RDRF will assert, but receive interrupt and DMA
Both TDRE and RDRF will be active.
MMEN = 1
MMEN = 1
, the BRG is enabled to generate SCK. If
, the BRG is enabled to generate SCK. If
ESPI Clock Phase and Polarity Control
ESPIEN1, ESPIEN0 = 00
P R E L I M I N A R Y
):
Enhanced Serial Peripheral Interface
MMEN = 0
MMEN = 0
on page 180.
Product Specification
, the BRG is
ZNEO
, the BRG is 
Z16F Series
194