Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 67

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
Table 16. External Interface Timing for a Read Operation - Normal Mode
Parameter
T
T
T
T
T
T
T
T
T
T
T
T
T
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
External Interface Read Timing - Normal Mode
Figure 13
performing a Read operation in NORMAL mode. In
the Wait state generator has been configured to provide 2 Wait states during Read
operations. For proper data hold time determination, you must know that the input data is
captured on chip during the rising edge of the system clock prior to the RD signal 
de-assertion. The Read signal (RD) timing is shown for both NORMAL and ISA modes.
Abbreviation
XIN Rise to Address Valid Delay
XIN Rise to Address Output Hold Time
Data Input Valid to XIN Rise Setup Time
RD Rise to Data Input Hold Time
XIN Rise to CS Assertion Delay
XIN Rise to CS Deassertion Hold Time
XIN Rise to RD Assertion Delay
XIN Rise to RD Deassertion Hold Time
WAIT Input Pin Assertion to XIN Rise Setup Time
WAIT Input Pin Deassertion to XIN Rise Setup Time
XIN Rise to DMAACK Assertion Delay
XIN Rise to DMAACK Deassertion Hold Time
XIN Rise to BHEN or BLEN Assertion Delay
XIN Rise to BHEN or BLEN Deassertion Hold Time
on page 53 and
Table 16
P R E L I M I N A R Y
provide timing information for the external interface
Figure 13
Minimum
on page 53, it is assumed
3
0
3
3
1
1
3
3
Product Specification
Delay (ns)
ZNEO
Maximum
External Interface
Z16F Series
10
10
10
10
10
3
52