Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 105

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
IRQ0 Enable High and Low Bit Registers
U1RXI—UART 1 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 1 receiver.
1 = An interrupt request from the UART 1 receiver is awaiting service. Writing 1 to this bit
U1TXI—UART 1 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service. Writing 1 to this
PWMFI— PWM Fault Interrupt Request
0 = No interrupt request is pending for the PWM fault.
1 = An interrupt request from the PWM fault is awaiting service. Writing 1 to this bit
PCxI/DMAxI—Port C Pin x or DMA x Interrupt Request
0 = No interrupt request is pending for GPIO port C pin x or DMA x.
1 = An interrupt request from GPIO port C pin x or DMAx is awaiting service. Writing 1
Where x indicates the specific GPIO port C pin or DMA number (0 through 3).
The IRQ0 enable high and low bit registers (see
encoded enabling for interrupts in the interrupt request 0 register. Priority is generated by
setting bits in each register.
Table 47. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]
0
0
1
1
Note: x indicates the register bits from 0 through 7.
Resets it to 0.
bit Resets it to 0.
Resets it to 0.
to this bit Resets it to 0.
IRQ0ENL[x]
P R E L I M I N A R Y
0
1
0
1
Table 47
describes the priority control for IRQ0.
Priority
Disabled
Level 1
Level 2
Level 3
Table 48
High
Description
Disabled
Low
Nominal
and
Table
Product Specification
ZNEO
49) form a priority
Interrupt Controller
Z16F Series
90