Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 339

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

®
ZNEO
Z16F Series
Product Specification
323
DBGHALT—Debug Halt mode
This status bit indicates if the CPU is stopped and in debug halt mode.
0 = Device is running
1 = CPU is in Debug Halt mode
DBGBRK—Debug break
This bit indicates if the CPU has reached a
instruction. This bit is set when a
BRK
BRK
instruction is executed. It is cleared when the DBGHALT control bit is written to zero.
HALT—HALT mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
STOP—STOP mode
0 = The device is not in Stop mode.
1 = The device is in Stop mode.
RPEN—Read protect enabled
0 = Memory Read Protect is disabled.
1 = Memory Read Protect is enabled.
TDRF—Transmit Data register full
This bit is set when the transmit data register is full.
0 = Transmit Data register is empty
1 = Transmit Data register is full
RDRE—Receive Data register empty
This bit indicates when the receive data register is empty.
0 = Receive Data register is full.
1 = Receive Data register is empty.
Reserved
These bits are reserved and always read back zero.
PS022008-0810
P R E L I M I N A R Y
On-Chip Debugger