Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 214
Z16F2800100ZCOG
Manufacturer Part Number
Z16F2800100ZCOG
Description
DEV KIT FOR Z16F ZNEO
Manufacturer
Zilog
Series
ZNEO™r
Type
MCUr
Datasheets
1.Z16F2800100ZCOG.pdf
(2 pages)
2.Z16F2800100ZCOG.pdf
(30 pages)
3.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2800100ZCOG
Contents
Evaluation Board, Software and Documentation
For Use With/related Products
Z16F Series
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4537
- Current page: 214 of 388
- Download datasheet (22Mb)
Table 103. ESPI State Register (ESPISTATE)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
ESPI State Register
SCKI
R
7
0
TFST—Transfer Status
0 = No data transfer is currently in progress.
1 = Data transfer is currently in progress.
SLAS—Slave Select
Reading this bit returns the current value of the SS exclusive-OR’d with the SSPO bit.
0 = SS pin is Low, if SSPO = 0, SS pin is High if SSPO = 1 (SS is asserted).
1 = SS pin is High, if SSPO = 0, SS pin is Low if SSPO = 1 (SS is deasserted).
The ESPI State register (see
internal state.
SCKI—Serial Clock Input
This bit reflects the state of the serial clock pin.
0 = The SCK input pin is Low
1 = The SCK input pin is High
SDI—Serial Data Input
This bit reflects the state of the serial data input (MOSI or MISO depending on the
bit).
0 = The serial data input pin is Low.
1 = The serial data input pin is High.
ESPISTATE—ESPI State Machine
Indicates the current state of the internal ESPI State Machine. This information is intended
for manufacturing test. The state values may change in future hardware revisions and are
not intended to be used by a software driver.
states.
SDI
R
6
0
5
P R E L I M I N A R Y
Table
103) provides observability of the ESPI clock, data, and
4
FF_E265H
Table 104
3
ESPISTATE
Enhanced Serial Peripheral Interface
R
0
on page 199 defines the valid
2
Product Specification
ZNEO
1
Z16F Series
MMEN
0
198
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