Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 120

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
Compare Mode Time (s)
6. Write to the timer control 1 register to enable the timer and initiate counting.
The compare time is calculated by the following equation (Start Value = 1):
GATED Mode
In GATED mode, the timer counts only when the timer input signal is in its active state as
determined by the TPOL bit in the timer control 1 register. When the timer input signal is
active, counting begins. A timer interrupt is generated when the timer input signal transits
from active to inactive state or a timer reload occurs. To determine if a timer input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the timer reload high and low byte
registers. On reaching the reload value, the timer generates an interrupt, the count value in
the timer high and low byte registers is Reset to
the timer input signal is active. If the timer output alternate function is enabled, the timer
output pin changes state (from Low to High or from High to Low) at timer reload.
Follow the steps below to configure a timer for GATED mode and initiate the count:
1. Write to the timer control registers to:
2. Write to the timer high and low byte registers to set the initial count value. This affects
3. Write to the timer reload high and low byte registers to set the Reload value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
5. Configure the timer interrupt to be generated only at the input deassertion event, the
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the timer control 1 register to enable the timer.
8. The timer counts when the timer input is equal to the TPOL bit.
–
–
–
–
only the first pass in GATED mode. After the first timer Reset in GATED mode,
counting always begins at the reset value of
interrupt registers.
reload event, or both by setting
Disable the timer
Configure the timer for GATED mode
Set the prescale value
Select the active state of the timer input through the TPOL bit
=
P R E L I M I N A R Y

----------------------------------------------------------------------------------------------------------------
Compare Value Start Value + 1
TICONFIG
System Clock Frequency (Hz)
field of the timer control 0 register.
–
0001H
0001H
.
and counting continues as long as
Product Specification

ZNEO

Prescale
Z16F Series
Timers
105