Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 205

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

®
ZNEO
Z16F Series
Product Specification
189
Receive Overrun
A receive overrun error occurs when a transfer completes and the RDRF bit is still set
from the previous transfer. A receive overrun sets the ROVR bit in the ESPI status register
to 1. Writing 1 to ROVR clears this error flag. The receive data register is not overwritten
and will contain the data from the transfer which initially set the RDRF bit. Subsequent
received data is lost until the RDRF bit is cleared.
Slave Mode Abort
In SLAVE mode of operation if the SS pin deasserts before all bits in a character have
been transferred, the transaction is aborted. When this condition occurs the ABT bit is set
in the ESPI Status register. A slave abort error resets the slave control logic to the idle
state.
A slave abort error is also asserted in SLAVE mode, if
and a BRG timeout
BRGCTL = 1
occurs. When
is in SLAVE mode, it functions as a WDT monitoring the SCK
BRGCTL = 1
signal. The BRG counter is reloaded every time a transition on SCK occurs while SS is
asserted. The baud rate reload registers must be programmed with a value longer than the
expected time between SS assertion and the first SCK edge, between SCK transitions
while SS is asserted and between the last SCK edge and SS deassertion. A timeout
indicates the master is stalled or disabled. Writing 1 to ABT clears this error flag.
ESPI Interrupts
ESPI has a single interrupt output which is asserted when any of the
,
,
,
TDRE
TUND
COL
,
, or
bits are set in the ESPI status register. The interrupt is a pulse
ABT
ROVR
RDRF
(duration of one system clock) generated when any one of the source bits initially set. The
TDRE and RDRF interrupts are enabled/disabled through the Data Interrupt Request
Enable (
) bit of the ESPI control register.
DIRQE
A transmit interrupt is asserted by the
status bit when the ESPI block is enabled and
TDRE
the
bit is set. The
bit in the status register is cleared automatically when the
DIRQE
TDRE
transmit data register is written or the ESPI block is disabled. When the Transmit Data
register value is loaded into the shift register to start a new transfer, the TDRE bit will be
set again causing a new transmit interrupt. If information is being received but not
transmitted the transmit interrupts are eliminated by selecting RECEIVE ONLY mode
(
). A master operates in Receive Only mode however a write to the ESPI
ESPIEN1,0 = 01
(Transmit) data register is still required to initiate the transfer of a character.
A receive interrupt is generated by the RDRF status bit when the ESPI block is enabled;
the
bit is set and a character transfer completes. At the end of the character transfer,
DIRQE
the contents of the shift register is transferred into the Receive Data register, causing the
bit to assert. The
bit is cleared when the Receive Data register is read. If
RDRF
RDRF
information is being transmitted but not received by the software application, the receive
interrupt is eliminated by selecting Transmit Only mode (
) in either
ESPIEN1,0 = 10
MASTER or SLAVE modes.
PS022008-0810
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface