Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 319

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Table 165. OCD Baud Rate Limits (Continued)
PS022008-0810
System Clock
Frequency
32.768 kHz
*
The maximum baud rate is limited by the rise and fall times due to the cable impedance.
Auto-Baud Detector
Line Control
To operate using various clock frequencies over a range of baud rates, the serial interface
has an auto-baud detector. The auto-baud detector is used to automatically setup the baud
rate generator.
The auto-baud detector is setup to measure one of two different auto-baud characters,
80H
Z8 Encore!
as a UART, you can switch to an auto-baud character of
ASCII carriage return character and is sent using a terminal interface.
When using the auto-baud character
the falling edge at the beginning of the start bit to the rising edge at the beginning of data
bit 7. For the auto-baud character
the rising edge at the end of the start bit to the rising edge at the beginning of the stop bit.
This measured value is automatically written to the BRG reload register once the 
auto-baud character is received. Once configured, the BRG will generate a bit clock based
on this measured character time.
When operating at high speeds, it is appropriate to speed up the rise and fall times of the
single wire bus. Three control bits are used to control the bus rise and fall times, the high
drive strength enable bit, the drive high enable bit, and the output enable control bit.
The high drive strength enable bit puts the pin into high drive mode. For information on
high drive strength, see
If the output enable control bit is set, the line is driven High and Low during transmission.
If the drive high control bit is set, it drives the line high for short periods when transmit-
ting a logic one. This rapidly charges the inherent capacitance of the single wire bus.
If both the output enable and drive high control bits are set, the line is driven high for one
clock cycle when transmitting a one. If the output enable bit is clear and the drive high bit
is set, the line is driven high until the input is detected High or the center of the bit time
occurs, whichever is first.
(default) or
®
debug interfaces. When the OCD is disabled and the DBG pin is being used
0DH
Baud Rate
4096 baud
Maximum
. The default auto-baud character
Electrical Characteristics
P R E L I M I N A R Y
0DH
80H
, the auto-baud detector measures the period from
Minimum Baud Rate
, the auto-baud detector measures the period from
(OCDEN=0)
4.0 baud
on page 337.
80H
0DH
is compatible with previous
. The
Product Specification
Minimum Baud Rate
0DH
ZNEO
(OCDEN=1)
character is the
On-Chip Debugger
64 baud
Z16F Series
303