Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 265

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Table 124. ADC0 Data Low Bits Register (ADC0D_L)
Table 125. Sample and Settling Time (ADCSST)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position Value (H) Description
[7:6]
[5:0]
Reserved
ADC0 Data Low Bits Register
Sample Settling Time Register
7
7
0
The ADC0 Data Low Bits register contains the lower bits of the ADC0 output. Access to
the ADC0 Data Low Bits register is Read-Only.
The sample settling time register is used to program the length of time from the SAMPLE/
HOLD signal to the START signal, when the conversion begins. The number of clock
cycles required for settling varies from system to system depending on the system clock
period used. You must program this register to contain the number of clocks required to
meet a 0.5 S minimum settling time.
00–11b
ADC0D_L
0
X
R
Reserved
ADC0 Low Bits
These bits are the 2 least significant bits of the 10-bit ADC0 output. These bits
are undefined after a Reset.
Reserved—Must Be 0.
R
6
6
0
5
5
0
P R E L I M I N A R Y
4
4
1
FF-E503H
FF-E504H
3
3
1
Reserved
X
R
SST
R/W
2
2
1
Product Specification
ZNEO
1
1
1
Analog Functions
Z16F Series
0
0
1
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