Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 65

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
Table 15. External Interface Timing for a Write Operation - ISA Mode
Parameter
T
T
T
T
T
T
T
T
T
T
T
T
T
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
External Interface Write Timing - ISA Mode
Figure 12
performing a Write operation. In
generator has been configured to provide 1 Wait state during Write operations. The
external WAIT input pin is generating an additional Wait period. As with the normal
mode, the WR signal is fed back from the pin and used on chip to time the removal of the
data signals to ensure proper timing of the data hold.
Abbreviation
XIN Rise to Address Valid Delay
XIN Rise to Address Output Hold Time
XIN Rise to Data Valid Delay
WR Rise to Data Output Hold Time
XIN Rise to CS Assertion Delay
XIN Rise to CS Deassertion Hold Time
XIN Fall to WR Assertion Delay
XIN Fall to WR Deassertion Hold Time
WAIT Input Pin Assertion to XIN Rise Setup Time
WAIT Input Pin Deassertion to XIN Rise Setup Time
XIN Rise to DMAACK Assertion Delay
XIN Rise to DMAACK Deassertion Hold Time
XIN Rise to BHEN or BLEN Assertion Delay
XIN Rise to BHEN or BLEN Deassertion Hold Time
on page 51 and
Table 15
P R E L I M I N A R Y
Figure 12
provide timing information for the external interface
on page 51, it is assumed that the Wait state
Minimum
3
3
3
3
1
1
3
3
Product Specification
Delay (ns)
ZNEO
External Interface
Maximum
Z16F Series
10
10
10
10
10
10
50