Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 159

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

®
ZNEO
Z16F Series
Product Specification
143
address byte. If the new frame’s address matches the LIN-UART’s, then the data in the new
frame is processed.
The second scheme is enabled by setting
to
and writing the LIN-UART’s
MPMD[1:0]
10b
address into the LIN-UART address compare register. This mode introduces more
hardware control, interrupting only on frames which match the address of LIN-UART.
When an incoming address byte does not match the address of LIN-UART, it is ignored.
All successive data bytes in this frame are also ignored. When a matching address byte
occurs, an interrupt is issued and further interrupts occur on each successive data byte. The
first data byte in the frame has
in the LIN-UART Status 1 register. When the
NEWFRM=1
next address byte occurs, the hardware compares it to the address of LIN-UART. If there is
a match, the interrupt occurs and the NEWFRM bit is set for the first byte of the new frame.
If there is no match, the LIN-UART ignores all incoming bytes until the next address
match.
The third scheme is enabled by setting
to
and by writing the address of
MPMD[1:0]
11b
LIN-UART into the LIN-UART address compare register. This mode is identical to the
second scheme, except that there are no interrupts on address bytes. The first data byte of
each frame remains accompanied by a
assertion.
NEWFRM
LIN Protocol Mode
The LIN protocol as supported by the LIN-UART module is defined in revision 2.0 of the
LIN specification package. The LIN protocol specification covers all aspects of transferring
information between LIN master and slave devices using message frames including error
detection and recovery, sleep mode, and wake up from sleep mode. The LIN-UART
hardware in LIN mode provides character transfers to support the LIN protocol including
Break transmission and detection, WAKE-UP transmission and detection, and slave
autobauding. Part of the error detection of the LIN protocol is for both master and slave
devices to monitor their receive data when transmitting. If the receive and transmit data
streams do not match, the LIN-UART asserts the PLE bit (physical layer error bit in status0
register). The message frame timeout aspect of the protocol is left to software, requiring the
use of an additional general purpose timer. The LIN mode of the LIN-UART does not
provide any hardware support for computing/verifying the checksum field or to verify the
contents of the identifier field. These fields are treated as data and are not interpreted by the
hardware.
The LIN bus contains a single master and one or more slaves. The LIN master is
responsible for transmitting the message frame header which consists of the Break, Synch,
and Identifier fields. Either the master or one of the slaves transmits the associated response
section of the message, which consists of data characters followed by a checksum
character.
PS022008-0810
P R E L I M I N A R Y
LIN-UART