Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 286

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

®
ZNEO
Z16F Series
Product Specification
270
Frames
A frame is a single buffer or a collection of buffers. Frame boundaries spans multiple 
buffers.
Source Address Register
The source address register (SAR) points to the data to be transferred. Each time a transfer
occurs the SAR is selected to stay fixed or increment/decrement by the size of the transfer
(example 1, 2, 4). If we were sending data to a serial channel, the SAR points to the data to
be transferred and the SAR would be set to increment or decrement depending on the
order of data in the buffer (ascending or desending).
Destination Address Register
The destination address register (DAR) points to the location to store the data transferred
from the address pointed to by the SAR. Each time a transfer occurs the DAR is selected
to stay fixed or increment/decrement by the size of the transfer (for example, 1, 2, and 4).
When sending data to a serial channel, the DAR points to the data register of the serial
channel and is set to a fixed address. Each transfer is then sent to the serial channel data
register since the DAR would not change.
Transfer Length
The transfer length register (TXLN) is used to specify how many transfers need to occur to
transfer this buffer. If we were sending bytes to a serial channel, the value of the number of
bytes in the buffer pointed to by the SAR would be placed in this register. Each time a
transfer takes place this register is decremented by one. When the transfer length 
decrements to zero, the buffer is complete and the DMA either stops or loads new control 
information and addresses (see linked list description).
List Address Register
The list address register (LAR) is only used for linked list mode. The LAR points to a list
of descriptors (described below). This descriptor list contains setup information for each
buffer the DMA is to transfer. Linked list DMAs reduce the amount of overhead on the
CPU to service the DMA.
Descriptor
A Descriptor is a 16 byte field in the memory space. It needs to be aligned on 16 byte
boundaries (that is lower 4-bits of address is 0).
Table 141
provides the descriptor format.
PS022008-0810
P R E L I M I N A R Y
DMA Controller