Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 107

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Table 51. IRQ1 Enable High Bit Register (IRQ1ENH)
Table 52. IRQ1 Enable Low Bit Register (IRQ1ENL)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
IRQ1 Enable High and Low Bit Registers
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
R/W
R/W
7
0
7
0
The IRQ1 enable high and low bit registers (see
encoded enabling for interrupts in the interrupt request 1 register. Priority is generated by
setting bits in each register.
Table 50. IRQ1 Enable and Priority Encoding
PADxENH—Port A/D Bit[x] Interrupt Request Enable High Bit.
PAxENL—Port A/D Bit[x] Interrupt Request Enable Low Bit.
IRQ1ENH[x]
0
0
1
1
Note: x indicates the register bits from 0 through 7.
R/W
R/W
6
0
6
0
IRQ1ENL[x] Priority
R/W
R/W
0
1
0
1
5
5
0
0
P R E L I M I N A R Y
Table 50
Disabled
Level 1
Level 2
Level 3
R/W
R/W
4
0
4
0
FF_E036H
FF_E037H
describes the priority control for IRQ1.
R/W
R/W
3
3
0
0
Table 51
Description
Disabled
Low
Nominal
High
and
R/W
R/W
2
0
2
0
Table
Product Specification
ZNEO
52) form a priority
R/W
R/W
Interrupt Controller
1
1
0
0
Z16F Series
R/W
R/W
0
0
0
0
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