Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 163

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
Note:
Transmitter Interrupts
The transmitter generates a single interrupt when the transmit data register empty bit
(
transmission. The TDRE interrupt occurs when the transmitter is initially enabled and after
the transmit shift register has shifted the first bit of a character out. At this point, the
transmit data register is written with the next character to send. This provides 7 bit periods
of latency to load the transmit data register before the transmit shift register completes
shifting the current character. Writing to the LIN-UART transmit data register clears the
TDRE bit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
In MULTIPROCESSOR mode (
the multiprocessor configuration and the most recent address byte.
•
•
•
•
LIN-UART Overrun Errors
When an overrun error condition occurs, the LIN-UART prevents overwriting of the valid
data currently in the receive data register. The break detect and overrun status bits are not
displayed until the valid data is read.
When the valid data is read, the OE bit of the Status0 register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the receive data register contains a data byte. However, because the overrun error occurred,
this byte may not contain valid data and must be ignored. The BRKD bit indicates if the
overrun is caused due to a break condition on the line. After reading the status byte
indicating an overrun error, the receive data register must be read again to clear the error
bits in the LIN-UART Status0 register.
In LIN mode, an overrun error is signaled for receive data overruns as described above and
in the LIN Slave, if the BRG counter overflows during the autobaud sequence (the
will also be set in this case). There is no data associated with the autobaud overflow
TDRE
A data byte is received and is available in the LIN-UART receive data register. This
A break is received.
A receive data overrun or LIN slave autobaud overrun error is detected.
A data framing error is detected.
A parity error is detected (physical layer error in LIN mode).
interrupt is disabled independent of the other receiver interrupt sources using the
RDAIRQ
interrupt occurs after the receive character is placed in the receive data register. To
avoid an overrun error, the software responds to this received data available condition
before the next character is completely received.
) is set to 1. This indicates that the transmitter is ready to accept new data for
bit (this feature is useful in devices, which support DMA). The received data
P R E L I M I N A R Y
MPEN
=
1
), the receive data interrupts are dependent on
Product Specification
ZNEO
Z16F Series
LIN-UART
ATB
bit
147