Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 290

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
DMA Modes
Loop Mode Closure
If the LOOP bit is set then the current buffer descriptor is not modified. The DMAxLAR
increments or a new LAR value is fetched from the descriptor.
EOF Closure
The
status data from the peripheral. If the channel is in linked list mode then the DMAxCTL
word is written back to the CONTROL word of the descriptor. The DMAxLAR 
increments or is loaded with new LAR data from the descriptor if the
Normal Closure
The
word is written back to the CONTROL word of the descriptor. The DMAxLAR 
increments or is loaded with new LAR data from the descriptor if the
Each DMA channel operates in two modes, direct and linked list. Both modes use the
DMA channel registers. The only difference is in how they are loaded. In direct mode
the DMA channel registers are directly loaded by software and when the transfer is done
the DMA stops. In linked list mode the DMA will load its own registers from a descrip-
tor list which is pointed to by the DMAxLAR register. It then loads the next descriptor in
the list and continue executing.
The descriptor Control/Status field and address bytes have the same format as the control
and address registers in the DMA.
Direct Mode
Direct mode only uses the registers in the DMA for operation. The software writes these
register directly to setup and enable the DMA. Direct mode is entered by directly setting
the DMAxEN bit in the DMAxCTL0 register.
registers and how they point to the buffers allocated in memory.
DMAxEN
DMAxEN
bit is reset to zero. If the channel is in linked list mode then the DMAxCTL
bit is reset to zero. If the
P R E L I M I N A R Y
EOF
bit is set, the CMDSTAT field is set with the
Figure 57
on page 275 displays the DMA
Product Specification
ZNEO
TXFR
TXFR
DMA Controller
bit is set.
bit is set.
Z16F Series
274