Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 285

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

DMA Description
PS022008-0810
DMA Register Description
The DMA is used to off load the processor from doing repetitive tasks. DMA transfers
data from one memory address to another memory address. Since all peripherals are
mapped in memory, the DMA transfers data to or from peripherals.
The DMA transfers data from the source address to the destination address. This requires a
read and/or write cycle that is generated by the DMA controller. Each DMA transfer
requires a minimum of two system clock cycles to execute.
The DMA operates in direct or linked list mode. Direct mode and Linked List mode are
almost the same. In Direct mode the software loads the DMA channel registers directly. In
linked list mode the DMA loads its registers from memory.
Each DMA channel consists of 16-bit control register, a 16-bit transfer length register, a
24-bit destination address register, a 24-bit source address register and a 24-bit list address
register (see
Buffers
A buffer is an allocation of contiguous memory bytes. Buffers are allocated by software to
be used by the DMA. The DMA transfers data to or from buffers. A typical application
would be to send data to serial channels such as I
placed in a buffer by software.
Figure
Figure 56. DMA Channel Registers
56).
P R E L I M I N A R Y
DMA Control (DMACTL)
Transfer Length (TXLN)
Destination Address (DAR)
Source Address (SAR)
List Address (LAR)
2
C, UART, and SPI. The data to be sent is
Product Specification
ZNEO
DMA Controller
Z16F Series
269