Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 117

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
2. Write to the timer high and low byte registers to set the starting count value (typically
3. Write to the PWM high and low byte registers to set the PWM value.
4. Write to the timer reload high and low byte registers to set the Reload value (PWM
5. Enable the timer interrupt, if required, and set the timer interrupt priority by writing to
6. Configure the associated GPIO port pin(s) for the timer output alternate function.
7. Write to the timer control 1 register to enable the timer and initiate counting.
The PWM period is determined by the following equation:
If an initial starting value other than
registers, use the ONE-SHOT mode equation to determine the first PWM timeout period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is determined
by:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is determined
by:
CAPTURE Modes
There are three CAPTURE modes which provide slightly different methods for recording
the time or time interval between timer input events. These modes are CAPTURE mode,
CAPTURE RESTART mode, and CAPTURE COMPARE mode. In all the three modes,
when the appropriate timer input transition (capture event) occurs, the timer counter value
is captured and stored in the PWM high and low byte registers. The TPOL bit in the timer
control 1 register determines if the Capture occurs on a rising edge or a falling edge of the
timer input signal. The TICONFIG bit determines whether interrupts are generated on
capture events, reload events, or both. The INCAP bit in timer control 0 register clears to
indicate an interrupt caused by a reload event and sets to indicate the timer interrupt is
caused by an input capture event.
PWM Period (s)
PWM Output High Time Ratio (%)
PWM Output High Time Ratio (%)
0001H
first timer reset in PWM mode, counting always begins at the reset value of
period). The Reload value must be greater than the PWM value.
the relevant interrupt registers.
). The starting count value only affects the first pass in PWM mode. After the
=
--------------------------------------------------------------------------- -
System Clock Frequency (Hz)
Reload Value Prescale
P R E L I M I N A R Y
0001H
=
=

Reload Value PWM Value
----------------------------------------------------------------------- -
--------------------------------- -
Reload Value
PWM Value
is loaded into the timer high and low byte
Reload Value
–

100
Product Specification
ZNEO

100
Z16F Series
0001H
Timers
.
102