Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 27

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Signal Descriptions
Table 2. Signal Descriptions
PS022008-0810
Signal Mnemonic
General-Purpose Input/Output Ports A–K
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
PF[7:0]
PG[7:0]
PH[3:0]
PJ[7:0]
PK[7:0]
External Interface
ADR[23:0]
DATA[15:0]
RD
Table 2
package styles, see
are multiplexed with GPIO pins. These signals are available as alternate functions on the
GPIO pins. For more details on the GPIO alternate functions, see
Output
on page 68.
describes the ZNEO signals. To determine the signals available for the specific
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
Pin Configurations
Description
Port A[7:0]: These pins are used for GPIO
Port B[7:0]: These pins are used for GPIO
Port C[7:0]: These pins are used for GPIO
Port D[7:0]: These pins are used for GPIO
Port E[7:0]: These pins are used for GPIO
Port F[7:0]: These pins are used for GPIO
Port G[7:0]: These pins are used for GPIO
Port H[3:0]: These pins are used for GPIO
Port J[7:0]: These pins are used for GPIO
Port K[7:0]: These pins are used for GPIO
Address bus: When the associated GPIO pins are configured for
alternate function and the external interface is enabled, these pins
function as output pin only. The address bus signals are driven to
0, when execution is out of internal program memory. The address
bus alternate functions are individually enabled and disabled.
Data bus: When the associated GPIO pins are configured for
alternate function and the external interface is enabled, these pins
functions as in put/output. The data bus alternate functions are
individually enabled and disabled. When Write operation is not
performed through the external interface, these signals are tri-
stated. The data bus is enabled as either 8-bits (DATA[7:0] only) or
16-bits (DATA[15:0]).
Read output: This pin is the Read output signal from the external
interface. Assertion of the RD signal indicates that the ZNEO CPU
is performing a Read operation from the external memory or
peripheral.
P R E L I M I N A R Y
on page 7. Most of the signals described in
Signal and Pin Descriptions
Product Specification
General-Purpose Input/
ZNEO
Z16F Series
Table 2
12