M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 106

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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R
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9.9 Address Match Interrupt
e
E
1
. v
Table 9.6 PC Value Saved in Stack Area When an Address Match Interrupt Request is Accepted
Table 9.7 Relationship Between Address Match Interrupt Sources and Associated Registers
J
6
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Op-code is an abbreviation of Operation Code. It is a portion of instruction code.
Refer to Chapter 4 Instruction Code/Number of Cycles in M16C/60, M16C/20 Series Software Manual. Op-code is shown
as a bold-framed figure directly below the Syntax.
Address match interrupt 0
Address match interrupt 1
0
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi
register. Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. The address
match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the PC that is
saved to the stack area varies depending on the instruction being executed (refer to “Saving Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Figure 9.13 shows the AIER, RMAD0 and RMAD1 registers.
C
• 2-byte op-code instruction
• 1-byte op-code instructions which are followed:
Instructions other than the above
Address match interrupt sources Address match interrupt enable bit
2
9
2 /
0 .
B
ADD.B:S
OR.B:S
STNZ.B
CMP.B:S
JMPS
MOV.B:S
0
0
8
0
G
4
J
7
a
o r
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8
#IMM,dest (However, dest=A0 or A1)
0
1
Instruction at the address indicated by the RMADi register
0
6
7
C
2 /
, 8
page 84
M
1
6
SUB.B:S
MOV.B:S
STZX.B
PUSHM
JSRS
C
2 /
f o
8
3
) B
8
5
AIER0
AIER1
#IMM8,dest
#IMM8,dest
#IMM81,#IMM82,dest
src
#IMM8
AND.B:S
STZ.B
POPM dest
#IMM8,dest
#IMM8,dest
RMAD0
RMAD1
Address match interrupt register
Value of the PC that is
saved to the stack area
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
9. Interrupts