M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 410

IC M16C/28 MCU FLASH 96K 80LQFP

M30280FAHP#U5B

Manufacturer Part Number
M30280FAHP#U5B
Description
IC M16C/28 MCU FLASH 96K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheets

Specifications of M30280FAHP#U5B

Core Size
16-Bit
Program Memory Size
96KB (96K x 8)
Core Processor
M16C/60
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Controller Family/series
M16C
No. Of I/o's
71
Ram Memory Size
8KB
Cpu Speed
20MHz
No. Of Timers
10
Digital Ic Case Style
LQFP
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Rev.
REVISION HISTORY
Date
74, 75
Page
101
110
111
113
114
115
116
117
126
127
128
64
68
70
71
72
75
76
77
83
90
• Figure 9.5 Time Required for Executing Interrupt Sequence note 2 added
• Figure 9.9 Hardware Interrupt Priority Watchdog timer added
• 9.6 INT Interrupt modified
• 9.7 NMI Interrupt modified
• 9.8 Key Input Interrupt modified
• 9.9 Address Match Interrupt modified
Watchdog Timer
• Figure 10.1 Watchdog Timer Block Diagram and Figure 10.2 WDC Register
• Figure 10.2 WDC Register and WDTS Register WDC Register: note 1 and
• 10.2 Cold Start/Warm Start added with Figure 10.3 Cold start/Warm start
DMAC
• note added
• Figure 11.5 Transfer Cycles for Source Read (2) is modified
Timer
• Figure 12.5 TA0 to TA4 Registers, TABSR Register, and UDF Register
• Figure 12.12 TAiMR Register in Pulse Width Modulation Mode b2 modified,
• Figure 12.23 TBiMR Register in A/D Trigger Mode Note 1 added
• Figure 12.24 TB2SC Register Reserved bit map modified
• Table 12.10 Three-phase Motor Control Timer Function Specifications
• Figure 12.26 INVC0 Register Note 1, 3, 5, 6 modified, note 10 deleted
• Figure 12.27 INVC1 Register INV13 bit modified, note 2 added, note 6 modi-
• Figure 12.28 IDB0 Register, IDB1 Register, DTT Register, and ICCTB2 Reg-
• Figure 12.29 TA1, TA2, TA4, TA11, TA21 and TA41 Register Values after
• Figure 12.30 TB2SC Register Reserved bit map modified
Timer S
• Figure 13.2 G1BT and G1BCR0 Register Values after reset modified,
• Figure 13.3 G1BCR1 Registers Value after reset modified, note 1 modified
• Figure 13.4 G1BTRR Register modified
and WDTS Register moved
note 2 modified
Operation Example
Timer Ai Register: note 3 modified
reserved bit map modified
Note 2 modified
fied
ister Values after reset modified, b7-6 in the ICTB2 register modified, reserved
bit map for the ICTB2 register modified
reset modified, note 6 modified
G1BCR0 Register: note 3 added
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M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
C-3
Description
Summary

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