M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 12

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10. Watchdog Timer ...........................................................................................86
11. DMAC ...........................................................................................................88
12. Timer ............................................................................................................98
9.2 Interrupts and Interrupt Vector ........................................................................................ 70
9.3 Interrupt Control .............................................................................................................. 72
9.4 Interrupt Sequence ......................................................................................................... 76
9.5 Interrupt Priority .............................................................................................................. 80
9.6 INT Interrupt ................................................................................................................... 82
9.7 NMI Interrupt ................................................................................................................... 83
9.8 Key Input Interrupt .......................................................................................................... 83
9.9 Address Match Interrupt ................................................................................................. 84
10.1 Count Source Protective Mode ..................................................................................... 87
11.1 Transfer Cycles ............................................................................................................ 93
11.2. DMA Transfer Cycles ................................................................................................... 95
11.3 DMA Enable .................................................................................................................. 96
11.4 DMA Request ................................................................................................................ 96
11.5 Channel Priority and DMA Transfer Timing .................................................................. 97
12.1 Timer A ...................................................................................................................... 100
9.2.1 Fixed Vector Tables .................................................................................................. 70
9.2.2 Relocatable Vector Tables ........................................................................................ 71
9.3.1 I Flag ........................................................................................................................ 75
9.3.2 IR Bit ........................................................................................................................ 75
9.3.3 ILVL2 to ILVL0 Bits and IPL...................................................................................... 75
9.4.1 Interrupt Response Time .......................................................................................... 77
9.4.2 Variation of IPL when Interrupt Request is Accepted ............................................... 77
9.4.3 Saving Registers ...................................................................................................... 78
9.4.4 Returning from an Interrupt Routine ......................................................................... 80
9.5.1 Interrupt Priority Resolution Circuit .......................................................................... 80
11.1.1 Effect of Source and Destination Addresses ......................................................... 93
11.1.2 Effect of Software Wait .......................................................................................... 93
12.1.1 Timer Mode .......................................................................................................... 103
12.1.2 Event Counter Mode ............................................................................................ 104
12.1.3 One-shot Timer Mode .......................................................................................... 109
12.1.4 Pulse Width Modulation (PWM) Mode ................................................................. 111
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