M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 227

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
Table 14.17 Registers to Be Used and Settings in IEBus Mode
NOTE:
. v
6
J
C
14.1.5 Special Mode 3 (IEBus mode)(UART2)
Register
U2TB
U2RB
U2BRG
U2MR
U2C0
U2C1
U2SMR
U2SMR2
U2SMR3
U2SMR4
0
2
9
2 /
In this mode, one bit in the IEBus is approximated with one byte of UART mode waveform.
Table 14.17 lists the registers used in IEBus mode and the register values set. Figure 14.30 shows the
functions of bus collision detect function related bits.
If the TxD2 pin output level and RxD2 pin input level do not match, a UART2 bus collision detect interrupt
request is generated.
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in IEBus
0 .
B
8
0
0
0
mode.
G
(1)
4
J
7
a
o r
0 -
. n
u
2
p
3
0
0 to 8
0 to 8
OER,FER,PER,SUM Error flag
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
0 to 3, 7
ABSCS
ACSE
SSS
0 to 7
0 to 7
0 to 7
, 1
0
(
M
2
1
0
Bit
0
6
7
C
2 /
, 8
page 205
M
1
6
C
2 /
f o
Set transmission data
Reception data can be read
Set a transfer rate
Set to ‘110
Select the internal clock or external clock
Set to “0”
Invalid because PRYE is set to "0"
Set to “0”
Select the TxD/RxD input/output polarity
Select the count source for the U2BRG register
Invalid because CRDis set to "1"
Transmit register empty flag
Set to “1”
Select TxD2 pin output mode
Set to “0”
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to “0”
Set to “0”
Set to “0”
8
3
) B
8
5
2
’
Function
14. Serial I/O