M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 115

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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11.1 Transfer Cycles
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The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write)
bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of
transfer. Furthermore, the bus cycle itself is extended by a software wait.
11.1.1 Effect of Source and Destination Addresses
11.1.2 Effect of Software Wait
Figure 11.5 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle
changing accordingly. When calculating transfer cycles, take into consideration each condition for the
source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit
units and when both the source address and destination address are an odd address ((2) in Figure 11.5),
two source read bus cycles and two destination write bus cycles are required.
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If the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source
read cycle consists of one more bus cycle than when the source address of transfer begins with an even
address.
Similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address,
the destination write cycle consists of one more bus cycle than when the destination address of transfer
begins with an even address.
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus
cycles required for that access increases by an amount equal to software wait states.
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11. DMAC