M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 111

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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1
NOTES:
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Table 11.1 DMAC Specifications
J
1. DMA transfer does not affect any interrupt. DMA transfer is not affected by the I flag nor by the interrupt
2. The selectable cause of DMA requests varies with each channel.
3. Do not access the DMAC-associated registers (addresses 0020
6
Reload timing for forward ad-
dress pointer and transfer
counter
0
No. of channels
Transfer memory space
Maximum No. of bytes transferred
DMA request factors
Channel priority
Transfer unit
Transfer address direction
Transfer mode Single transfer
value
DMA interrupt request generation timing When the DMAi transfer counter underflowed
DMA startup
the
DMA shutdown Single transfer
C
2
9
control register.
0 .
2 /
B
0
0
8
0
4
G
J
7
a
o r
0 -
. n
u
2
3
p
0
, 1
0
Item
(
M
2
0
1
Repeat transfer When the DMAE bit is set to “0” (disabled)
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the
0
6
7
C
2 /
(1, 2)
, 8
page 89
M
1
6
C
f o
2 /
8
3
) B
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrupt requests
A/D conversion interrupt requests
Timer S(IC/OC) requests
Software triggers
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer is completed when the DMAi transfer counter (i = 0,1)
underflows after reaching the terminal count.
tinued with it.
• When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
When a data transfer is started after setting the DMAE bit to “1” (en
abled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Data transfer is initiated each time a DMA request is generated when
8
of the DMAi transfer counter reload register and a DMA transfer is con
DMAiCON register’s DMAE bit = “1” (enabled).
5
________
________
________
________
Specification
16
to 003F
16
) with DMAC.
11. DMAC