M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 214

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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R
R
1
e
E
6
Figure 14.22 I
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J
C
0
2
9
2 /
0 .
SDA2
B
SCL2
8
0
0
IICM
IICM2, SWC, ALS, SWC2, SDHI : Bits in the UiSMR2 register
STSPSEL, ACKD, ACKC
NOTES:
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register is set to "010
register is set to "1".
0
G
4
1. If the IICM bit is set to "1", the pin can be read even when the PD7_1 bit is set to "1" (output mode).
J
7
o r
a
0 -
. n
u
2
p
3
0
, 1
0
(
M
Filter
Noise
2
2
C bus Mode Block Diagram
1
0
6
0
Noise
Filter
7
C
2 /
Delay
circuit
ACKC=1
, 8
ACKD bit
IICM=1
page 192
IICM=0
M
Falling edge
detection
1
UART2
6
: Bits in the UiSMR register
: Bits in the UiSMR4 register
STSPSEL=0
C
I/O port
STSPSEL=1
STSPSEL=0
Start condition
detection
Stop condition
detection
ACKC=0
2 /
f o
8
STSPSEL=1
3
) B
8
D
5
T
Q
Q
R
SDHI
Arbitration
Port register
(1)
Internal clock
External
clock
ALS
SWC2
S
R
S
R
CLK
control
SCL
SDA
Q
Start and stop condition generation block
Reception register
Transmission
register
9th bit falling edge
STSP
Bus
busy
STSP
UART2
UART2
UART2
SWC
9th bit
D
D
T
T
Q
Q
IICM2=1
ACK
2
" and the IICM bit in the UiSMR
IICM=1 and
IICM2=0
IICM2=1
IICM=1 and
IICM2=0
NACK
Start/stop condition
detection interrupt
request
UART2 transmit,
NACK interrupt
request
DMA0, DMA1 request
(UART1: DMA0 only)
DMA0
(UART0, UART2)
UART2 receive,
ACK interrupt request,
DMA1 request
14. Serial I/O