M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 303

IC M16C/28 MCU FLASH 96K 80LQFP

M30280FAHP#U5B

Manufacturer Part Number
M30280FAHP#U5B
Description
IC M16C/28 MCU FLASH 96K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheets

Specifications of M30280FAHP#U5B

Core Size
16-Bit
Program Memory Size
96KB (96K x 8)
Core Processor
M16C/60
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Controller Family/series
M16C
No. Of I/o's
71
Ram Memory Size
8KB
Cpu Speed
20MHz
No. Of Timers
10
Digital Ic Case Style
LQFP
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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R
R
M
e
E
1
. v
J
6
Figure 16.24 The time of generation of RESTART condition
0
(2) Generation of RESTART condition
C
2
9
(3) Iimitation of CPU clock
0 .
2 /
B
S
S
S1I writing signal
( START condition setting standby)
S0I writing signal
(START condition trigger generation)
enter START condition standby mode and leave the SDA
by setting the S00 register after inserting a sufficient software wait until the SDA
("H") signal. Figure 16.24 shows the RESTART condition generation timing.
0
0
In order to generate a RESTART condition after 1-byte data transfer, write “E0
8
CL
DA
0
When the CM07 bit in the CM0 register is set to "1" (subclock), each register of the I
circuit cannot be read or written. Read or write data when the CM07 bit is set to "0" (main clock, PLL
clock, or on-chip oscillator clock).
4
G
J
7
a
o r
0 -
. n
u
2
3
p
0
, 1
0
(
8 clock
M
2
0
1
0
6
7
C
2 /
page 281
, 8
M
1
6
C
f o
2 /
8
3
) B
8
5
ACK
clock
MM
Insert software wait
open. Generate a START condition trigger
16. MULTI-MASTER I
MM
16
” to the S10 register,
outputs a high-level
2
2
C bus INTERFACE
C bus interface

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