M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 418

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev.
REVISION HISTORY
Date
135-142
144-159
282-285
Page
124
138
163
169
180
207
211
215
220
231
240
247
249
250
251
255
263
269
294
296
Timer
• Figure 12.28 IDB0 Register, IDB1 Register, DTT Register, and ICTB2 Regis-
Timer S
• Figure 13.5 G1TMCR0 to G1TMCR7 Registers Note 4 is modified
• Figure 13.2 to 13.9 Notes and description are modified
• Table 13.2, 13.5, 13,8, 13.9 and 13.10 Output wave form and Selectable func-
Serial I/O
• Note is modified
• Figure 14.6 U0C0 to U2C0 Registers Note 2 is modified
• 14.1.1.7 CTS/RTS separate function (UART0) modified
• Figure 14.31 Transmit and Received Timing in SIM Mode partially modified
• Figure 14.36 S3C and S4C Registers Note 5 is added
• Figure 14.36 S3BRG and S4BRG Registers Note 3 is added
A/D Converter
• Note is modified
• Figure 15.5 TB2SC Register Reserved bit map is modified
• Table 15.8 Simultaneous Sample Sweep Mode Specifications Pin number
• Table 15.12 Delayed Trigger Mode 1 Specifications Note 1 is modified
• Figure 15.29 Analog Input Pin and External Sensor Equivalent Circuit Note
Multi-master I
• Figure 16.1 Block Diagram of Multi-master I
• Figure 16.2 S0D0 Register Bit symbol is modified
• Figure 16.3 S00 Register Note is modified
• Figure 16.7 S4D0 Register Bit reserved map is modified
• 16.5.6 Bit 5: Bus Busy Flag (BB) Bit names are modified
• 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) is modified
• 19.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN) is
Programmable I/O Ports
• Figure 17.1 I/O Ports (1) to Figure 17.4 I/O Ports (4) are modified
Flash Memory Version
• Table 18.1 Flash Memory Version Specifications Specifications of program/
• Figure 18.1 to Figure 18.3 Flash Memory Block Diagrams Information added
ter Information of bit 7 and 6 is changed
tion are modified
in Note 1 is modified
1 is added
register name are modified
modified
erase endurance and protect method are partially modified; note 2 is modified
_______ _______
M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
2
C bus INTERFACE
C-11
Description
Summary
2
C bus Interface Bit name and