M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 380

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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20.4.6 Rewrite the Interrupt Control Register
20.4.7 Watchdog Timer Interrupt
C
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(1) The interrupt control register for any interrupt should be modified in places where no requests for that
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, due to the internal bus and the instruction queue buffer.
Example 1: Using the NOP instruction to keep the program waiting until the
Example 2:Using the dummy read to keep the FSET instruction waiting
Example 3:Using the POPC instruction to changing the I flag
Initialize the watchdog timer after the watchdog timer interrupt occurs.
0 .
B
Changing any bit other than the IR bit
Changing the IR bit
0
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8
INT_SWITCH1:
The number of NOP instruction is as follows.
PM20 = 1 (1 wait) : 2, PM20 = 0 (2 waits): 3
INT_SWITCH2:
INT_SWITCH3:
0
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-
quested). Therefore, be sure to use the MOV instruction to clear the IR bit.
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
instruction to be used.
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
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FCLR
AND.B
NOP
NOP
FSET
FCLR
AND.B
MOV.W
FSET
PUSHC
FCLR
AND.B
POPC
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3
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interrupt control register is modified
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#00h, 0055h
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#00h, 0055h
MEM, R0
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FLG
I
#00h, 0055h
FLG
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; Disable interrupts
;Set the TA0IC register to 00
;
; Enable interrupts
; Disable interrupts
; Set the TA0IC register to 00
; Dummy read
; Enable interrupts
; Disable interrupts
; Set the TA0IC register to 00
; Enable interrupts
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20. Precautions