M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 195

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
. v
6
Figure 14.8 U2SMR and U2SMR2 Registers
J
0
C
2
9
2 /
0 .
B
8
0
0
NOTES:
UART2 Special Mode Register
0
b7 b6 b5 b4 b3 b2 b1 b0
G
UART2 Special Mode Register 2
4
b7 b6 b5 b4 b3 b2 b1 b0
J
1: The BBS bit is set to “0” by writing “0" by program. (Writing “1” has no effect).
2: When a transfer begins, the SSS bit is set to “0” (Not synchronized to R
7
a
o r
0 -
. n
u
2
p
3
0
, 1
0
(
M
2
1
0
0
0
6
7
C
2 /
, 8
page 173
M
ABSCS
Symbol
ACSE
1
SSS
ABC
(b3)
(b7)
BBS
IICM
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
Symbol
6
Bit
(b7)
C
Bit
2 /
f o
Symbol
U2SMR2
8
I
Arbitration lost detecting
flag control bit
Bus busy flag
Reserved bit
Bus collision detect
sampling clock select bit
Auto clear function
select bit of transmit
enable bit
Transmit start condition
select bit
3
2
Nothing is assigned. When write, set “0”.
When read, its content is indeterminate.
) B
Symbol
U2SMR
C bus mode select bit
8
I C bus mode select bit 2
Clock-synchronous bit
SCL
SDA
UART initialization bit
SCL
SDA
Nothing is assigned. When write, set “0”.
When read, its content is indeterminate.
2
5
2
2
2
2
Bit Name
wait output bit
wait output bit 2
output stop bit
output disable bit
Bit Name
Address
0376
Address
0377
16
0 : Rising edge of transfer clock
1 : Underflow signal of timer A0
0 : Not synchronized to R
1 : Synchronized to R
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
16
0 : Other than I
1 : I
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Set to “0”
Refer to Table 14.13
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: Transfer clock
1: “L” output
0: Enabled
1: Disabled (high impedance)
2
C bus mode
X
After Reset
X0000000
Di).
2
C bus mode
After Reset
X0000000
2
X
Di
X
(2)
Function
Di
2
Function
RW
RW
RW
RW
RW
RW
RW
RW
(1)
14. Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW