M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 218

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
6
Figure 14.23 Transfer to U2RB Register and Interrupt Timing
. v
J
C
0
2
9
2 /
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"
0 .
B
(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)
SCL2
SDA2
SCL2
SDA2
SCL2
SDA2
SCL2
SDA2
(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"
8
0
0
0
The above timing applies to the following setting :
• The CKDIR bit in the U2MR register is set to "1" (slave)
G
4
J
7
o r
a
0 -
. n
u
2
p
3
0
, 1
0
(
1st
1st
1st
bit
M
bit
bit
1st
bit
D
D
D
2
D
1
0
7
7
7
7
6
0
7
C
2nd
2nd
2nd
2nd
bit
bit
bit
bit
2 /
D
D
D
D
, 8
6
6
6
page 196
6
M
3rd
3rd
3rd
bit
3rd
bit
bit
bit
1
D
D
D
D
6
5
5
5
5
C
2 /
4th
4th
4th
bit
f o
bit
bit
4th
Data is transferred to the U2RB register
bit
D
D
D
Data is transferred to the U2RB register
8
D
3
4
4
4
) B
b15
4
8
5
•••
5th
5th
5th
bit
bit
bit
5th
bit
D
D
D
b9
D
Contents of the U2RB register
3
3
3
3
D
b8
0
6th
6th
6th
bit
bit
bit
6th
b7
bit
D
D
D
D
D
Data is transferred to the U2RB register
2
2
2
Data is transferred to the U2RB register
2
7
Receive interrupt
(DMA request)
D
Receive interrupt
(DMA request)
6
7th
7th
7th
bit
7th
bit
bit
bit
D
D
D
D
D
5
1
1
1
D
1
4
D
8th
8th
8th
bit
bit
bit
8th
3
bit
ACK interrupt (DMA
request) or NACK interrupt
ACK interrupt (DMA
request) or NACK interrupt
D
D
D
D
D
0
2
0
0
0
D
b0
1
9th
9th
9th
bit
9th
bit
bit
D
bit
D
D
D
8
8
8
Transmit interrupt
b15
b15
8
Data is transferred to the U2RB register
(ACK or NACK)
(ACK or NACK)
(ACK or NACK)
(ACK or NACK)
Transmit interrupt
•••
•••
b9
b9
Contents of the U2RB register
Contents of the U2RB register
D
D
b8
b8
8
0
D
b7
b7
7
D
D
6
7
b15
D
D
5
6
•••
•••
D
D
4
5
b15
Contents of the U2RB register
Contents of the U2RB register
D
b9
D
3
4
D
D
D
b8
D
8
8
2
3
b9
D
D
D
b7
D
7
7
1
2
D
D
b8
D
D
b0
b0
6
6
0
1
D
D
b7
5
5
D
D
4
4
D
D
3
3
D
D
2
2
14. Serial I/O
D
D
1
1
D
D
b0
b0
0
0