M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 141

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
Figure 12.21 Operation timing when measuring a pulse period
Figure 12.22 Operation timing when measuring a pulse width
6
. v
J
C
0
2
9
2 /
0 .
B
i = 0 to 2
NOTES:
TBiS bit
The MR3 bit in the
TBiMR register
Measurement pulse
Timing at which counter
reaches “0000
TBiMR register's
MR3 bit
TBiS bit
TBiIC register's
IR bit
NOTES:
TBiIC register's
IR bit
Reload register
transfer timing
Count source
Measurement pulse
Timing at which counter
reaches “0000
i = 0 to 2
Reload register
transfer timing
8
0
0
0
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00
G
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “10
4
J
7
o r
interval from falling edge to falling edge of the measurement pulse).
a
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
0 -
. n
u
Count source
2
p
3
0
, 1
(
0
M
2
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
16
16
1
0
”
6
”
0
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
7
C
counter
counter
2 /
, 8
page 119
“H”
“1”
“0”
“1”
“0”
“1”
“0”
“L”
“H”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
M
1
6
C
2 /
f o
8
3
) B
8
5
Set to “0” upon accepting an interrupt request or by program
Set to “0” upon accepting an interrupt request or by
program
Transfer
(indeterminate
value)
(1)
Transfer
(measured value)
(1)
Transfer
(indeterminate value)
(1)
Transfer
(measured
value)
(1)
Transfer
(measured value)
(1)
Transfer
(measured value)
(1)
2
” (measure the interval
2
” (measure the
(1)
(2)
12. Timer