M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 118

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
11.3 DMA Enable
11.4 DMA Request
e
E
1
. v
6
J
Peripheral function
DMA factor
Software trigger
Table 11.4 Timing at Which the DMAS Bit Changes State
0
C
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
If the DMAi is not in an initial state, the above steps should be repeated.
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS
and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 11.4 shows the timing at
which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set
to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a
program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
2
9
2 /
0 .
B
(a) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register
(b) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
(1) Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
(2) Make sure that the DMAi is in an initial state as described above (a) and (b) by program.
0
8
0
0
G
4
J
is “1” (forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward).
7
a
o r
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
0
1
0
6
7
C
2 /
, 8
page 96
When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits in the DMiSL register
has its IR bit set to “1”
When the DSR bit in the DMiSL
register is set to “1”
M
Timing at which the bit is set to “1”
1
6
C
2 /
f o
8
3
) B
8
5
DMAS bit of the DMiCON register
• Immediately before a data transfer starts
• When set by writing “0” in a program
Timing at which the bit is set to “0”
11. DMAC