M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 399

IC M16C/28 MCU FLASH 96K 80LQFP

M30280FAHP#U5B

Manufacturer Part Number
M30280FAHP#U5B
Description
IC M16C/28 MCU FLASH 96K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheets

Specifications of M30280FAHP#U5B

Core Size
16-Bit
Program Memory Size
96KB (96K x 8)
Core Processor
M16C/60
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Controller Family/series
M16C
No. Of I/o's
71
Ram Memory Size
8KB
Cpu Speed
20MHz
No. Of Timers
10
Digital Ic Case Style
LQFP
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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20.14.14 Definition of Programming/Erasure Times
20.14.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle products (U7, U9)
20.14.16 Boot Mode
20.14.17 Standard Serial I/O Mode
C
2
9
2 /
"Number of programs and erasure" refers to the number of erasure per block.
If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times.
For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different
address, this is counted as one program and erasure. However, data cannot be written to the same
adrress more than once without erasing the block. (Rewrite prohibited)
If the number of Block A or B E/W cycle is already known to exceed 100, set the FMR17 bit in the FMR1
register to "1" (one wait) after reset. When the FMR17 bit is set to "1", one wait state is inserted per
access to Block A or B, regardless of the value of the PM17 bit in the PM1 register. Wait state insertion
during access to all other blocks, as well as to internal RAM, is controlled by PM17, regardless of the
setting of FMR17.
To use the limited number of erasure efficiently, write to unused address within the block instead of
rewrite. Erase block only after all possible address are used. For example, an 8-word program can be
written 128 times before erase becomes necessary.
Maintaining an equal number of erasure between Block A and B will also improve efficiency.
We recommend keeping track of the number of times erasure is used and limiting the number of erasure.
An indeterminate value is sometimes output in the I/O port until the internal power supply becomes stable
when "H" is applied to the CNV
When setting the CNV
When the CNV
In flash memory version (128 K + 4 K), a high-level ("H") signal is output from P9
in standard serial I/O mode. In standard serial I/O mode, input an "H" signal to P9
open.
0 .
B
0
0
8
0
G
4
J
7
a
o r
0 -
. n
(1) Apply an "L" signal to the RESET pin and the CNV
(2) Bring V
(3) Apply an "H" signal to the CNV
(4) Apply an "H" signal to the RESET pin.
u
2
3
p
0
, 1
0
(
M
2
0
1
0
6
SS
7
C
CC
2 /
pin is “H” and RESET pin is “L”, P6
page 377
, 8
to more than 2.7V, and wait at least 2msec. (Internal power supply stable waiting time)
M
SS
1
6
pin to "H", the following procedure is required:
C
2 /
f o
8
3
) B
SS
8
____________
5
pin and "L" is applied to the RESET pin.
____________
____________
SS
pin.
7
pin is connected to the pull-up resister.
SS
_____________
pin.
3
for certain period of time
3
or leave the port
20. Precautions

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