M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 392

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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8. If the CPU reads the AD register i (i = 0 to 7) at the same time the conversion result is stored in the AD
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register
10. When setting the ADST bit in the ADCON register to "0" to stop A/D conversion during A/D converting
0 .
B
0
0
register i after completion of A/D conversion, an incorrect value may be stored in the AD register i. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
to “0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents
of AD register i irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all AD register i.
operation in single sweep conversion mode, A/D delayed trigger mode 0, or A/D delayed trigger mode 1,
set the ADST bit to "0" after an interrupt is disabled because the A/D interrupt request may be generated.
8
0
• When operating in one-shot, single-sweep mode, simultaneous sample sweep mode, delayed
• When operating in repeat mode or repeat sweep mode 0 or 1
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Check to see that A/D conversion is completed before reading the target AD register i. (Check the IR
bit in the ADIC register to see if A/D conversion is completed.)
Use the main clock for CPU clock directly without dividing it.
7
trigger mode 0 or delayed trigger mode 1
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page 370
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20. Precautions