M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 239

IC M16C/28 MCU FLASH 96K 80LQFP

M30280FAHP#U5B

Manufacturer Part Number
M30280FAHP#U5B
Description
IC M16C/28 MCU FLASH 96K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheets

Specifications of M30280FAHP#U5B

Core Size
16-Bit
Program Memory Size
96KB (96K x 8)
Core Processor
M16C/60
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Controller Family/series
M16C
No. Of I/o's
71
Ram Memory Size
8KB
Cpu Speed
20MHz
No. Of Timers
10
Digital Ic Case Style
LQFP
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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M
R
R
15. A/D Converter
1
e
E
NOTES:
. v
6
J
Table 15.1 A/D Converter Performance
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10
AN
shares the pin with P1
bits are set to “0” (input mode). Note that P1
the 80-pin package.
When not using the A/D converter, set the VCUT bit to “0” (Vref unconnected), so that no current will flow
from the Vref pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register bits for AN
Table 15.1 shows the A/D converter performance. Figure 15.1 shows the A/D converter block diagram
and Figures 15.2 to 15.4 show the A/D converter associated with registers.
A/D Conversion Method
Analog Input Voltage
Operating Clock f
Resolution
Integral Nonlinearity Error When AV
Operating Modes
Analog Input Pins
Conversion Speed Per Pin
0
C
2
9
1. Analog input voltage does not depend on use of sample and hold function.
2. Set the AD frequency to 10 MHz or less. For M16C/28B, set it to 12 MHz or less.
2 /
0 .
B
Ports P0
available in M16C/28 (64-pin package). Do not use port P0
to AN2
7
Note
0
8
0
), P0
Without sample-and-hold function, set the AD frequency to 250kH
With the sample and hold function, set the AD frequency to 1MH
0
G
4
J
7
a
o r
0 -
. n
0
Item
u
3
2
to P0
p
3
) and P9
0
4
, 1
0
(
M
to P0
2
1
0
7
AD
0
6
(AN0
7
C
(2)
7
(1)
2 /
5
(AN0
to P9
page 217
, 8
0
5
. Therefore, when using these inputs, make sure the corresponding port direction
M
to AN0
4
1
7
to AN0
6
0V to AV
f
or f
• With 8-bit resolution: 2LSB
• With 10-bit resolution: 3LSB
When AV
• With 8-bit resolution: 2LSB
• With 10-bit resolution: 5LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
8 pins (AN
8 pins (AN
• Without sample and hold function
• With sample and hold function
(AN2
Successive approximation (capacitive coupling amplifier)
8-bit or 10-bit (selectable)
AD
C
8-bit resolution: 49
8-bit resolution: 28
2 /
f o
/divided-by-2 or f
AD
7
8
), and P1
5
3
) B
/divided-by-12 or f
7
8
to AN2
), P1
5
0
CC
CC
CC
0
to AN
to AN
0
(V
= Vref = 5V
= Vref = 3.3V
to P1
0
7
CC
) as analog input pins in M16C/28 (64-pin package.).
7
to P1
) + 8 pins (AN0
7
0
)
) + 4 pins (AN0
to P1
3
(AN2
AD
3
, P9
AD
AD
/divided-by-3 or f
3
AD
, P9
cycles, 10-bit resolution: 59
cycles, 10-bit resolution: 33
0
3
, P9
to AN2
3
0
, P9
to AN0
5
0
to P9
Performance
to AN0
5
3
4
) and P9
to P9
to P0
7
) + 8 pins (AN2
7
i
, AN0
3
(AN2
) + 1 pin (AN2
AD
7
7
(AN0
(AN2
/divided-by-4 or f
Z
5
i
Z
0
, and AN2
or more.
to P9
to AN2
or more.
4
0
to AN0
to AN2
0
7
to AN2
(AN2
4
7
)
). Similarly, AD
AD
AD
i
7
pins (i = 0 to 7).
7
), P1
7
(64pin package)
5
) are available only in
cycles
cycles
) (80pin/85pin package)
to AN2
AD
0
0
/divided-by-6
to P1
to P10
15. A/D Converter
____________
7
) are not
3
(AN2
TRG
7
(AN
input
0
0
to

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