M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 258

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Table 15.10 Delayed Trigger Mode 0 Specifications
NOTES:
J
6
A/D Conversion Start
Readout of A/D Conversion Result Readout one of the AN0 to AN7 registers that corresponds to the selected
Function
A/D Conversion Stop
Condition
Interrupt Request
Generation Timing
Analog Input Pin
0
15.1.7 Delayed Trigger Mode 0
C
2
9
In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a
digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The
Timer B0 underflow starts a single sweep conversion. After completing the AN
pin is not sampled and converted until the Timer B1 underflow is generated. When the Timer B1 under-
flow is generated, the single sweep conversion is restarted with the AN
delayed trigger mode 0 specifications. Figure 15.19 shows the operation example in delayed trigger
mode 0. Figures 15.20 and 15.21 show each flag operation in the ADSTAT0 register that corresponds to
the operation example. Figure 15.22 shows the ADCON0 to ADCON2 registers in delayed trigger mode
0. Figure 15.23 shows the ADTRGCON register in delayed trigger mode 0 and Table 15.11 shows the
trigger select bit setting in delayed trigger mode 0.
1. Set the larger value than the value of the timer B0 register to the timer B1 register. The count source for
2. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 0. When write “1”,
3. AN0
0 .
2 /
B
0
0
8
timer B0 and timer B1 must be the same.
unexpected interrupts may be generated.
need to belong to the same group.
0
4
G
J
7
a
o r
0 -
. n
0
Item
u
2
to AN0
3
p
0
, 1
0
(
M
2
0
1
0
6
7
7
C
and AN2
2 /
page 236
, 8
M
1
6
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits
in the ADCON2 register select pins. Analog voltage applied to the input voltage of
the selected pins are converted one-by-one to the digital code. At this time, Timer B0
underflow generation starts AN
starts conversion after the AN
AN
AN
A/D conversion completed
Select from AN
and AN
pins
0
C
•When single sweep conversion from the AN
•Set the ADST bit to "0" (A/D conversion halted)
•When Timer B0 underflow is generated if Timer B0 underflow is generated again
•When Timer B1 underflow is generated during A/D conversion of the AN
to AN2
•When Timer B0 underflow is generated during A/D conversion of pins after the
sweep start when AN
before Timer B1 underflow is generated , the conversion is not affected
AN
input voltage of the AN
f o
2 /
0
1
pin conversion start condition
pin conversion start condition
8
3
1
) B
8
pin, conversion is halted and the sweep is restarted from the AN
5
0
7
to AN
can be used in the same way as AN
7
0
(8 pins)
to AN
0
conversion is completed.
1
1
(3)
(2 pins), AN
pin is sampled. The AN
Specification
1
0
pin.
pin conversion. Timer B1 underflow generation
(1)
0
to AN
3
(4 pins), AN
1
0
0
conversion and the rest of the
to AN
pin is completed
1
(2)
pin. Table 15.10 shows the
0
7
pin conversion, the AN
. However, all input pins
0
to AN
15. A/D Converter
0
5
pin again
(6 pins)
0
pin, the
1