M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 69

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
e
E
1
Figure 7.3 CM1 Register
Figure 7.4 ROCR Register
. v
J
6
0
C
2
9
0 .
2 /
B
0
0
8
0
NOTES:
On-chip Oscillator Control Register
4
G
NOTES:
J
b7
b7
7
System Clock Control Register 1
a
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
o r
0 -
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
2. When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
3. Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
4. If the CM10 bit is “1” (stop mode), X
5. After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), wait until tsu (PLL) elapses before setting the CM11 bit to
6. When the PM21 bit in the PM2 register is set to “1” (clock modification disable), writing to the CM10, CM11 bits has no effect.
7. Effective when CM07 bit is “0” and CM21 bit is “0” .
. n
b6
0
b6
u
pins are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the CM2 register
is set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
When the PM22 bit in the PM2 register is set to “1” (watchdog timer count source is on-chip oscillator clock), writing to the
2
“1” (PLL clock).
CM10 bit has no effect.
speed mode, the CM15 bit is set to “1” (drive capability high).
3
p
0
, 1
b5
0 0
0
b5
(
M
b4
2
0 0
b4
0
1
0
b3
6
7
b3
C
b2
0
2 /
b2
b1
, 8
page 47
b0
b1
M
1
Bit Symbol
b0
6
(b4-b2)
C
CM15
CM16
CM17
CM10
CM11
Symbol
CM1
f o
2 /
Bit Symbol
ROCR0
ROCR1
ROCR2
ROCR3
8
(b6-b4)
3
) B
(b7)
8
Symbol
OUT
ROCR
5
All clock stop control bit
(4, 6)
Main clock division
select bits
System clock select bit 1
(6, 7)
Reserved bit
X
select bit
(1)
goes “H” and the internal feedback resistor is disconnected. The X
IN
-X
OUT
Frequency Select Bits
Divider Select Bits
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
Reserved Bit
(2)
drive capacity
Name
(3)
Bit
(1)
Address
0007
Bit Name
16
Address
025C
After Reset
00100000
0 : Main clock
1 : PLL clock (Note 5)
0 : Clock on
1 : All clocks off (stop mode)
Set to
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
0 : LOW
1 : HIGH
16
“0”
2
0 0 : f
0 1 : f
1 0 : Do not set to this value
1 1 : f
Set to “0”.
b1 b0
0 0 : Do not set to this value
0 1 : divide by 2
1 0 : divide by 4
1 1 : divide by 8
b3 b2
After Reset
X0000101
1
2
3
(ROC)
(ROC)
(ROC)
Function
Function
2
7. Clock Generation Circuit
CIN
and X
COUT
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW