M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 117

IC M16C/28 MCU FLASH 96K 80LQFP

M30280FAHP#U5B

Manufacturer Part Number
M30280FAHP#U5B
Description
IC M16C/28 MCU FLASH 96K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheets

Specifications of M30280FAHP#U5B

Core Size
16-Bit
Program Memory Size
96KB (96K x 8)
Core Processor
M16C/60
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Controller Family/series
M16C
No. Of I/o's
71
Ram Memory Size
8KB
Cpu Speed
20MHz
No. Of Timers
10
Digital Ic Case Style
LQFP
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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R
R
M
11.2. DMA Transfer Cycles
e
E
1
NOTES:
. v
J
k
6
j
Table 11.2 DMA Transfer Cycles
Table 11.3 Coefficient j, k
0
C
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
1. Depends on the set value of PM20 bit in PM2 register
2
9
Internal ROM, RAM
No wait With wait
Any combination of even or odd transfer read and write adresses is possible. Table 11.2 shows the
number of DMA transfer cycles. Table 11.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
0 .
2 /
Transfer unit
B
0
0
8
1
1
0
4
G
J
7
a
o r
0 -
. n
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
u
2
3
p
0
Internal area
, 1
0
(
2
2
M
2
0
1
0
6
7
C
Access address
2 /
1 wait
, 8
page 95
(1)
2
2
M
Even
Even
SFR
Odd
Odd
1
6
C
2 wait
f o
2 /
(1)
3
3
8
3
) B
8
5
No. of read cycles
1
1
1
2
No. of write cycles
1
1
1
2
11. DMAC

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