M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 384

IC M16C/28 MCU FLASH 96K 80LQFP

M30280FAHP#U5B

Manufacturer Part Number
M30280FAHP#U5B
Description
IC M16C/28 MCU FLASH 96K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheets

Specifications of M30280FAHP#U5B

Core Size
16-Bit
Program Memory Size
96KB (96K x 8)
Core Processor
M16C/60
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Controller Family/series
M16C
No. Of I/o's
71
Ram Memory Size
8KB
Cpu Speed
20MHz
No. Of Timers
10
Digital Ic Case Style
LQFP
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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M
R
R
e
E
1
. v
J
6
0
C
2
9
2 /
0 .
B
20.6.1.4 Timer A (Pulse Width Modulation Mode)
0
0
8
0
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
4. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
G
4
J
7
a
o r
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
listed changes have been made.
• Stop counting.
• When TAi
• When TAi
(three-phase output forcible cutoff by input on SD pin enabled), the TA1
pins go to a high-impedance state.
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
0
1
0
6
7
C
OUT
OUT
2 /
page 362
, 8
pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
pin is output “L”, both output level and the IR bit remains unchanged.
M
1
6
C
2 /
f o
8
3
) B
8
5
_____
_____
OUT
, TA2
OUT
20. Precautions
and TA4
OUT

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