M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 386

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
e
E
1
. v
J
6
0
20.6.3 Three-phase Motor Control Timer Function
C
2
9
2 /
When the IVPCR1 bit in the TB2SC register is set to 1 (three-phase output forced cutoff by SD pin input
(high-impedance) enabled), the INV03 bit in the INVC0 register is set to 1 (three-phase motor control
timer output enabled), and a low-level ("L") signal is applied to the SD pin while a three-phase PWM
signal is output, the MCU is forced to cutoff and pins U, U, V, V, W, and W are placed in a high-impedance
state and the INV03 bit is set to 0 (three-phase motor control timer output disabled).
To resume the three-phase PWM signal output from pins U, U, V, V, W, and W, set the INV03 bit to 1 and
the IVPCR1 bit to 0 (three-phase output forced cutoff disabled) after the SD pin level becomes "H". Then
set the IVPCR1 bit to 1 (three-phase output forced cutoff enabled) in order to enable the three-phase
output forced cutoff function by input to the SD pin again.
The INV03 bit cannot be set to 1 while an "L" signal is input to the SD pin. To set the INV03 bit to 1 after
forcible cutoff, write 1 to the INV03 bit and read the bit to ensure that it is set to 1 by program. Then set the
IVPCR1 bit to 1 after setting it to 0.
0 .
B
0
0
8
0
6. When a count is started and the first effective edge is input, an indeterminate value is transferred to
7. A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and timer
8. For pulse width measurement, pulse widths are successively measured. Use program to check
G
4
J
7
a
o r
the reload register. At this time, timer Bi interrupt request is not generated.
Bi interrupt request may be generated between a count start and an effective edge input.
whether the measurement result is an “H” level width or an “L” level width.
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
0
1
0
6
7
C
2 /
page 364
, 8
M
1
6
C
2 /
f o
8
3
) B
8
5
___
___
___
___
_____
_____
___
_____
___
20. Precautions