M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 14

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16. Multi-master I
15.2 Resolution Select Function ......................................................................................... 248
15.3 Sample and Hold ........................................................................................................ 248
15.4 Power Consumption Reducing Function .................................................................... 248
15.5 Output Impedance of Sensor under A/D Conversion ................................................. 249
16.1 I
16.2 I
16.3 I
16.4 I
16.5 I
16.6 I
15.1.3 Single Sweep Mode ............................................................................................ 227
15.1.4 Repeat Sweep Mode 0 ......................................................................................... 229
15.1.5 Repeat Sweep Mode 1 ......................................................................................... 231
15.1.6 Simultaneous Sample Sweep Mode .................................................................... 233
15.1.7 Delayed Trigger Mode 0 ....................................................................................... 236
15.1.8 Delayed Trigger Mode 1 ....................................................................................... 242
16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) ..................................... 260
16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE) .............................................. 260
16.3.3 Bit 6: ACK Bit (ACKBIT) ...................................................................................... 260
16.3.4 Bit 7: ACK Clock Bit (ACK-CLK) .......................................................................... 260
16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2) ..................................................................... 262
16.4.2 Bit 3: I
16.4.3 Bit 4: Data Format Select Bit (ALS) ..................................................................... 262
16.4.4 Bit 6: I
16.4.5 Bit 7: I
16.5.1 Bit 0: Last Receive Bit (LRB) ............................................................................... 264
16.5.2 Bit 1: General Call Detection Flag (ADR0) .......................................................... 264
16.5.3 Bit 2: Slave Address Comparison Flag (AAS) ..................................................... 264
16.5.4 Bit 3: Arbitration Lost Detection Flag (AL) ........................................................... 264
16.5.5 Bit 4: I
16.5.6 Bit 5: Bus Busy Flag (BB) .................................................................................... 265
16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX) ....... 266
16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) ................ 266
16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM ) ......................................... 267
16.6.2 Bit 1: Interrupt Enable Bit at the Completion of Data Receive (WIT) .................. 267
16.6.3 Bits 2,3 : Port Function Select Bits PED, PEC .................................................... 268
2
2
2
2
2
2
C0 Data Shift Register (S00 register) ....................................................................... 259
C0 Address Register (S0D0 register) ....................................................................... 259
C0 Clock Control Register (S20 register) ................................................................ 260
C0 Control Register 0 (S1D0) ................................................................................. 262
C0 Status Register (S10 register) ........................................................................... 264
C0 Control Register 1 (S3D0 register) .................................................................... 267
2
2
2
2
C Interface Enable Bit (ES0) .................................................................... 262
C bus Interface Reset Bit (IHR) ............................................................... 262
C bus Interface Pin Input Level Select Bit (TISS) .................................... 263
C bus Interface Interrupt Request Bit (PIN) ............................................. 265
2
C bus Interface ....................................................................250
A-5