M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 116

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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1
Figure 11.5 Transfer Cycles for Source Read
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2
9
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B
0
8
0
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
(3) When the source read cycle under condition (1) has one wait state inserted
(4) When the source read cycle under condition (2) has one wait state inserted
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address.
0
CPU clock
CPU clock
CPU clock
CPU clock
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4
WR signal
WR signal
WR signal
WR signal
Address
bus
RD signal
Data
bus
Address
bus
RD signal
Data
bus
Address
bus
RD signal
Data
bus
Address
bus
RD signal
Data
bus
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7
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NOTES:
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2
1. The same timing changes occur with the respective conditions at the destination as at the source.
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2
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1
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6
7
C
CPU use
CPU use
CPU use
2 /
CPU use
CPU use
, 8
CPU use
CPU use
CPU use
page 94
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6
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8
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Source
8
Source
5
Source
Source
Source
Source
Source + 1
Source
Source
Destination
Source + 1
Destination
Destination
Destination
Source + 1
Destination
Destination
Source + 1
Dummy
cycle
Dummy
cycle
Dummy
cycle
Dummy
cycle
Destination
Dummy
cycle
Dummy
cycle
Destination
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
Dummy
cycle
Dummy
cycle
CPU use
CPU use
11. DMAC