M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 143

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
Figure 12.23 TBiMR Register in A/D Trigger Mode
Figure 12.24 TB2SC Register in A/D Trigger Mode
6
. v
J
C
0
2
9
2 /
0 .
B
8
0
0
0
G
4
J
7
o r
a
0 -
. n
u
2
p
3
0
Timer B2 special mode register
b7
, 1
NOTES:
(
0
Timer Bi Mode Register (i= 0 to 1)
M
b7
NOTE:
2
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), set the PD8_5
4. Associated pins are U(P8
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1" (A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]),
7. Refer to "17.6 Digital Debounce Function" for the SD input
b6
0 0
1
0
1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
b6
bit to "0" (timer B2 underflow).
bit to "0" (= input mode).
to the SD pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-
impedance state. If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will
be disabled (INV03=0). At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become
programmable I/O ports. When the IVPCR1 bit is set to 1, pins U, U, V, V, W, and W are placed in a high-
impedance state regardless of which function of those pins is used.
set the INV02 bit to "1" (three-phase motor control timer function).
6
0
b5
7
C
b5
2 /
b4
b4
, 8
page 121
b3
1 1
b3
M
b2
b2
1
6
b1
b1
0
C
b0
2 /
b0
0
f o
8
Bit Symbol
Bit Symbol
3
IVPCR1
) B
PWCON
TB2SEL
(b6-b5)
TB0EN
TB1EN
TMOD0
TMOD1
8
0
TCK0
TCK1
MR0
MR1
MR2
MR3
(b7)
), U(P8
Symbol
TB2SC
5
Symbol
TB0MR to TB1MR
1
), V(P7
Three-Phase Output Port
SD Control Bit 1
Timer B0 Operation Mode
Select Bit
Timer B1 Operation Mode
Select Bit
Timer B2 Reload Timing
Switch Bit
Trigger Select Bit
Operation mode select bit
Invalid in A/D trigger mode
Either "0" or "1" is enabled
TB0MR register
Set to “0” in A/D trigger mode
TB1MR register
Nothing is assigned. When write, set to “0”.
When read, the content is indeterminate
When write in A/D trigger mode, set to “0”. When read in A/D
trigger mode, its content is indeterminate.
Count source select bit
(1)
Reserved bits
Nothing is assigned. When write, set to “0”.
When read, the content is “0”
Address
2
039E
), V(P7
Bit Name
Bit Name
(2)
16
3
), W(P7
(3, 4, 7)
Address
039B
(6)
4
16
(1)
), W(P7
to 039C
0 : TB2 interrupt
1 : Underflow of TB2 interrupt generation
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
0 : Three-phase output forcible cutoff
1 : Three-phase output forcible cutoff
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : Other than A/D trigger mode
1 : A/D trigger mode
X0000000
After Reset
Set to "0"
0 0 : Timer mode or A/D trigger mode
b7 b6
0 0 : f
0 1 : f
1 0 : f
1 1 : f
b1 b0
frequency setting counter [ICTB2]
by SD pin input (high impedance)
disabled
by SD pin input (high impedance)
enabled
5
). When a high-level ("H") signal is applied
16
1
8
32
C32
or f
2
2
After Reset
00XX0000
Function
Function
2
(5)
(5)
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
12. Timer