M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 197

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Table 14.1 Clock Synchronous Serial I/O Mode Specifications
NOTES:
. v
6
J
14.1.1 Clock Synchronous serial I/O Mode
Interrupt request
generation timing
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
Error detection
Select function
0
C
2
9
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register is set to “0”
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains unchanged.
3. The U0IRS and U1IRS bits respectively are the bits 0 and 1 in the UCON register; the U2IRS bit is bit 4 in the U2C1 register.
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1
lists the specifications of the clock synchronous serial I/O mode. Table 14.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
2 /
0 .
B
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external
clock is in the high state; if the CKPOL bit in the UiC0 register is set to “1” (transmit data output at the rising edge and the
receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
8
0
0
0
G
4
J
7
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0 -
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Item
2
p
3
0
, 1
0
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2
1
0
0
6
7
C
2 /
, 8
page 175
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• Transfer data length: 8 bits
• The CKDIR bit in the UiMR(i=0 to 2) register is set to “0” (internal clock) : fj/ (2(n+1))
• CKDIR bit is set to “1” (external clock ) : Input from CLKi pin
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met
_
_
_
• Before reception can start, the following requirements must be met
_
_
_
• For transmission, one of the following conditions can be selected
_
_
• For reception
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
• Switching serial data logic (UART2)
• Transfer clock output from multiple pins selection (UART1)
• Separate CTS/RTS pins (UART0)
• UART1 pin remapping selection
C
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
fj = f
UiTB register to the UARTi transmit register (at start of transmission)
data from the UARTi transmit register
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit in the the next data
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
Reception is enabled immediately by reading the UiRB register
The output pin can be selected in a program from two UART1 transfer clock pins that
The UiIRS bit
The TE bit in the UiC1 register is set to "1" (transmission enabled)
The TI bit in the UiC1 register is set to "0" (data present in UiTB register)
If CTS function is selected, input on the CTSi pin is set to “L”
The RE bit in the UiC1 register is set to "1" (reception enabled)
The TE bit in the UiC1 register is set to "1" (transmission enabled)
The TI bit in the UiC1 register is set to "0" (data present in the UiTB register)
The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending
_________
have been set
CTS
The UART1 pin can be selected from the P6
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
2 /
f o
This function reverses the logic value of the transmit/receive data
_______
8
3
1SIO
) B
0
8
and RTS
5
, f
_______ _______
2SIO
_________
(3)
(2)
, f
0
8SIO
_______
is set to "0" (transmit buffer empty): when transferring data from the
are input/output from separate pins
, f
32SIO
. n: Setting value of UiBRG register
_______
Specification
_______
7
to P6
_______ _______
4
or P7
3
to P7
0
00
(1)
16
(1)
to FF
14. Serial I/O
16