M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 172

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
Figure 13.17 Base Timer Reset operation by INT1
Figure 13.15 Base Timer Reset operation by Base Timer Reset Register
Figure 13.16 Base Timer Reset operation by G1PO0 register
. v
6
J
13.1.1 Base Timer Reset Register(G1BTRR)
0
C
2
9
2 /
0 .
B
NOTE:
8
0
0
0
1. INT1 Base Timer reset does not generate a Base Timer interrupt,INT1 may generate an interrupt if enabled.
The G1BTRR register provides the capability to reset the base timer when the base timer count value
matches the value stored in the G1BTRR register. The G1BTRR register is enabled by the RST4 bit in
the G1BCR0 register. This function is identical in operation to the G1PO0 base timer reset that is
enabled by the RST1 bit in the G1BCR0 reigster. If the free-running operation is not selected, the
channel 0 can be used for a waveform generation when the base timer is reset by the G1BTRR
register. Do not enable the RST1 bit and RST4 bit simultaneously.
G
4
J
Base timer overflow request
NOTE:
________
7
a
o r
0 -
. n
1. Following conditions are required to generate a base timer overflow request by resetting the base timer.
u
2
p
3
0
, 1
0
(
If the IT bit is set to 0: 07FFF
If the IT bit is set to 1: 07FFF
M
Base timer reset
2
G1BTRR register
(Base timer reset register)
Base timer
Base timer
1
0
0
6
G1PO0
G1IR0
RST1
7
C
P8
RST2
2 /
Base timer
3
page 150
, 8
/INT1
M
RST4
1
6
C
2 /
f o
8
3
) B
8
(1)
5
16
16
m 0FFFE
m
m - 2
m - 2
0FFFE
_______
m - 2
m - 1
16
16
m - 1
or 0BFFF
m - 1
m
________
16
m
m
m 0FFFE
m + 1 0000
m
m + 1 0000
m
m + 1 0000
16
16
16
0001
0001
16
16
16
0001
16
13. Timer S