M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 184

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
1
e
E
Figure 13.24 Set/Reset Waveform Output Mode
. v
6
J
0
C
2
9
2 /
0 .
B
8
0
0
0
G
(1) Free-running operation
(2) Base timer is reset when the base timer matches either following register
4
J
7
a
o r
0 -
. n
(Bits RST2 and RST1 in the G1BCR0 register and the RST4 bit in the G1BCR1
(a) G1PO0 (enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or
(b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0)
u
2
register are set to 0)
p
3
0
G1IRk bit
Base timer
Base timer
The above applies under the following conditions.
G1IRk bit
OUTC1j pin
G1IRj bit
OUTC1j pin
G1IRj bit
The above applies under the following conditions.
, 1
0
(
M
2
The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0
Bits UD1 and UD0 are set to 00
The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0 (not
inversed).
Bits UD1 and UD0 are set to 00
(not inversed).
1
0
0
6
7
C
2 /
FFFF
0000
j=0, 2, 4, 6 k=j+1
m : Setting value of the G1POj register
G1IRj, G1IRk bits: Bits in the G1IR register
page 162
FFFF
0000
j=2, 4, 6 k=j+1
m : Setting value of the G1POj register
p: Setting value of either register G1PO0 or G1BTRR
G1IRj, G1IRk bits: Bits in the G1IR register
, 8
p+2
M
16
m
16
n
16
16
m
n
1
6
C
2 /
f o
8
3
) B
8
5
n-m
f
n-m
BT1
f
2
2
BT1
Inverse
(counter increment mode).
(counter increment mode).
Write 0 by program
if setting to 0
Write 0 by program
if setting to 0
p+2-n+m
65536
f
BT1
f
When setting to 0,
write 0 by program
BT1
65536-n+m
inverse
f
BT1
n: Setting value of the G1POk register
n: Setting value of the G1POk register
Inverse
Return to default
output level
Return to default output level
13. Timer S