M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 196

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
e
E
1
Figure 14.9 U2SMR3 and U2SMR4 Registers
. v
J
6
0
C
2
9
2 /
0 .
B
0
8
0
0
NOTES:
UART2 Special Mode Register 3
b7 b6 b5 b4 b3 b2 b1 b0
G
4
J
7
a
o r
UART2 Special Mode Register 4
0 -
b7 b6 b5 b4 b3 b2 b1 b0
. n
NOTE:
1. The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I
2. The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
u
2
3
p
I
delay increases by about 100 ns.
0
2
1. Set to “0” when each condition is generated.
, 1
C bus mode, set these bits to “000
0
(
M
2
0
1
0
6
7
C
2 /
page 174
, 8
M
1
Symbol
CKPH
NODC
6
(b0)
(b2)
(b4)
DL0
DL1
DL2
C
Bit
2 /
f o
Bit Symbol
RSTAREQ
STSPSEL
STPREQ
Symbol
U2SMR3
STAREQ
8
SCLHI
ACKD
ACKC
SWC9
3
) B
8
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Clock phase set bit
Clock output select bit
SDA digital delay
setup bit
(1, 2)
5
Symbol
U2SMR4
2
" ( UART mode transfer data 9 bits long).
Bit Name
Restart condition
generate bit
Stop condition
SCL
ACK data bit
ACK data output
SCL
SCL
Start condition
generate bit
2
2
2
, SDA
Bit Name
output stop
wait bit 3
Address
0375
Address
0374
2
(1)
output
16
(1)
16
b7 b6 b5
0 : Without clock delay
1 : With clock delay
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
0: Clear
1: Start
0: Clear
1: Start
0: Clear
1: Start
0: Start and stop conditions not output
1: Start and stop conditions output
0: ACK
1: NACK
0: Serial I/O data output
1: ACK data output
0: Disabled
1: Enabled
0: SCL
1: SCL
After Reset
00
After Reset
000X0X0X
2
2
16
“L” hold disabled
“L” hold enabled
Function
2
Function
2
C bus mode. In other than
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
14.Serial I/O