M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 231

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
e
E
1
. v
Figure 14.31 Transmit and Receive Timing in SIM Mode
J
6
0
C
2
9
0 .
2 /
B
0
0
8
(1) Transmit Timing
Transfer Clock
TE bit in U2C1
register
TI bit in U2C1
register
TxD
Parity Error Signal
returned from
Receiving End
RxD
TXEPT bit in U2
C0 register
IR bit in S2TIC
register
Transfer Clock
RE bit in U2C1
register
Transmit Waveform
from the
Transmitting End
TxD2
RxD
RI bit in U2C1
register
IR bit in S2RIC
register
0
NOTES:
(2) Receive Timing
4
G
The above timing diagram applies to the case where data is
transferred in the direct format.
The above timing diagram applies to the case where data is
transferred in the direct format.
J
7
a
2
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
2
2
o r
1. Because TxD
2. Because TxD
0 -
. n
pin Level
pin Level
u
signal sent back from receiver.
and the parity error signal received.
2
3
p
0
, 1
0
(
M
2
(1)
(2)
0
1
0
6
7
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
C
"1"
"0"
"1
"0
"0
"
"
"
2
2
2 /
and RxD
and RxD
page 209
, 8
M
1
ST
ST
ST
Start
ST
Start
2
2
bit
6
bit
are connected, this is composite waveform consisting of the TxD
are connected, this is composite waveform consisting of the transmitter's transmit waveform
C
D
D
D
D
0
0
f o
2 /
0
0
D
D
D
D
8
3
1
1
1
1
) B
8
TC
Tc
D
D
D
D
5
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
D
D
5
5
5
5
D
D
D
D
Data is written to
the UARTi register
6
6
6
6
D
D
D
D
7
7
7
7
Parity
Parity
bit
P
P
bit
P
P
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
SP
SP
SP
SP
Stop
Stop
bit
fi : frequency of U2BRG count source (f
f
n : value set to U2BRG
fi : frequency of U2BRG count source (f
f
n : value set to U2BRG
bit
EXT
EXT
Set to "0" by an interrupt request acknowledgement or by program
Set to "0" by an interrupt request acknowledgement or by program
: frequency of U2BRG count source (external clock)
: frequency of U2BRG count source (external clock)
ST
ST
ST
ST
An interrupt routine
detects "H" or "L"
Data is transferred from the U2TB
register to the UART2 transmit
register
An "L" signal is applied from the SIM
card due to a parity error
D
D
D
D
0
0
0
0
Read the U2RB register
D
D
D
D
1
1
1
1
D
D
D
D
2
2
2
2
EXT
EXT
D
TxD
to a parity error
D
D
D
3
3
3
3
2
2
D
D
D
D
outputs "L" due
4
4
4
4
output and the parity error
An interrupt routine detects
"H" or "L"
D
D
D
D
5
5
5
5
1SIO
1SIO
D
D
D
D
6
6
6
6
, f
, f
D
D
D
D
2SIO
2SIO
7
7
7
7
P
P
P
P
, f
, f
8SIO
8SIO
SP
SP
SP
SP
, f
, f
32SIO
32SIO
)
)
14. Serial I/O