M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 292

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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16.7 I
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6
Figure 16.13 The timing of time-out detection
0
The S4D0 register controls the error communication detection.
If the SCL clock is stopped counting dring data transfer, each device is stopped, staying online. To avoid
the situation, the I
stopped in high-level ("H") state for a specific period, and to generate an I
See Figure 16.13.
C
2
9
0 .
B
2 /
Internal counter stop, reset signal
0
Internal counter overflow signal
0
8
0
2
4
Internal counter start signal
J
G
I
2
7
C-BUS interface interrupt
a
C0 Control Register 2 (S4D0 Register)
o r
0 -
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u
2
3
0
p
, 1
0
(
request signal
M
2
0
1
0
BB flag
6
7
C
S
S
2
DA
CL
2 /
C bus interface circuit has a function to detect the time-out when the SCL clock is
page 270
, 8
M
1
6
C
f o
2 /
8
3
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8
5
1 bit
1 clock
2 bit
2 clock
3 bit
16. MULTI-MASTER I
3 clock
2
The time of timeout detection
C bus interface interrupt request.
S
CL
clock stop (“H”)
2
C bus INTERFACE